1. Field of the Invention
The present invention generally relates to a method for fabricating field effect transistors (FETs) with fin structure. More particularly, the present invention relates to a method for fabricating a field effect transistor having a fin structure with rounded top edges.
2. Description of the Prior Art
With the trend in the industry being towards scaling down the size of metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, and accordingly, the channel region is more effectively controlled. The drain-induced barrier lowering (DIBL) effect and short channel effect is therefore reduced. The channel region is also longer under the same gate length, and thus the current between the source and the drain is increased. In addition, threshold voltage of the fin FET can further be controlled by adjusting the work function of the gate.
In a conventional three-dimensional structure of the FET with fin structure, sharp corners or edges generally lie between the top surface and the sidewalls of the fin structure, which cause a higher electrical field strength to accumulate in these sharp corners or edges. Generally speaking, the non-uniform distribution of the electrical field may cause carriers at the gate channel region to move at different speeds, therefore reducing the electrical performance of the device. Furthermore, if electrical field strength is over the maximum sustaining ability of the gate insulation layer, structures around the gate insulation layer will collapse, thereby reducing the reliability of the device.
In order to overcome the above-mentioned drawbacks, there is a need to provide a novel method for fabricating a fin FET which can avoid the accumulation of the electrical field and therefore improve the reliability of a semiconductor device.